[REQ ID-11508]{P-R} Need - ASIC Design/Verification Engineer

Hello,

Very Good Evening! Hope you are doing well!

We have the below job opportunity. Please find the details below.

Position: ASIC Design/Verification Engineer
Duration: 12+ months, extendable
Levels: Intermediate / Senior

Location I: San Jose / Santa Clara, CA
Location II: Boise, ID
Location III: Longmont, CO

Description:

Around 4 to 7 years of demonstrable industrial experience ASIC/SoC verification experience. FPGA verification also can be considered
Must be very well-versed with hands-on Verilog coding, testbenches.
Experience with SystemVerilog verification (OVM or UVM) methodology
Scripting languages, e.g. – Perl, Tcl, Python or Shell scripting

Thanks & Regards
Vineetha Nath
Office: 678-250-9864
Email: vineethat@systelcomputers.com

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